VTS_01_1
Schematic Entry, Buiding the example Test design, Analog Simulation with Spectre.
Mr. Kumaravel, Research Scholar NIT-T
VTS_01_2
Symbol Creation, Creating a layout view.
Mr. Kumaravel, Research Scholar NIT-T
VTS_01_3
Physical verification.
Mr. Kumaravel, Research Scholar NIT-T
VTS_01_4
Lab Session with Cadence Spectre and ADE.
Mr. Kumaravel and Mr. Swaminathan, Research Scholar NIT-T
VTS_01_5
Lab Session with Cadence Spectre and ADE.
Mr. Parthiban, M.Tech Student, NIT-T
VTS_01_1_2
Lab Session with Cadence Spectre and ADE.
Mr. Parthiban, M.Tech Student, NIT-T
VTS_01_2_2
Layout Considerations for Analog Circuits.
Dr. Laxminidhi, Assistant Professor NIT-Surathkal
VTS_01_3_2
Layout Considerations for Analog Circuits.
Dr. Laxminidhi, Assistant Professor NIT-Surathkal
VTS_01_4_2
Layout Considerations for Analog Circuits
Dr. Laxminidhi, Assistant Professor NIT-Surathkal
VTS_01_5_2
Layout Considerations for Analog Circuits
Dr. Laxminidhi, Assistant Professor NIT-Surathkal
VTS_01_1_3
RTL to GDS Flow.
Mr. Prasanna Kumar, Research Scholar IIT Kanpur
VTS_01_2_3
RTL to GDS Flow. Mr. Prasanna Kumar, Research Scholar IIT Kanpur
VTS_01_3_3
Digital Design Flow.
Prof. Ramesh Kini, Professor NIT-Surathkal
VTS_01_4_3
Digital Design Flow.
Prof. Ramesh Kini, Professor NIT-Surathkal
VTS_01_5_3
Digital Design Flow.
Prof. Ramesh Kini, Professor NIT-Surathkal
VTS_01_1_4
Digital Design Flow.
Prof. Ramesh Kini, Professor NIT-Surathkal
VTS_01_2_4
Digital Design Flow.
Prof. Ramesh Kini, Professor NIT-Surathkal
VTS_01_3_4
RTL to GDS Flow (Back End Flow).
Mrs. Shavitha Shenoy Mangalore & Mr. Prasanna Kumar
VTS_01_4_4
RTL to GDS Flow (Back End Flow).
Mrs. Shavitha Shenoy Mangalore & Mr. Prasanna Kumar
VTS_01_5_4
Digital lab Session (Back End).
Mrs. Shavitha Shenoy Mangalore & Mr. Prasanna Kumar
VTS_01_3_3
Integrating digital design with analog design.
Dr. Laxminidhi & Prof. Ramesh Kini

VTS_01_4_3

VTS_01_5_3
Sharing of Integration Experience.
Mr. Naveen/Diptiman (IBM Bangalore)
VTS_01_1_4
Steps in sending various files to IMEC, Measured results from previous tapeout.
Dr. Ramasamy, RMK EC
VTS_01_2_4
Working with memory compiler (FARADAY).
Mr. Mangesh, Mr. Sreenath (Intel)