|
Instruction Enhancement Programme |
Name of the Institute |
Date |
Topic |
No. of participants attended |
IISc Bangalore |
Dec 4-15, 2006 |
|
18 |
IIT Kanpur |
Dec 10-21, 2007 |
|
25 |
| IISc Bangalore |
Mar 10-19,2008 |
|
24 |
| CEERI Pilani |
Oct 14-18, 2008 |
Linux System Administration and EDA Tools Installation
|
26 |
| GEC,Goa (Conducted by IIT-Bombay ) |
March 16-21, 2009 |
Mixed-Signal VLSI Design |
33 |
Thapar University-
Patiala
(Organised by
CEERI-Pilani) |
December 14-23,2009 |
System Modeling Using System C/VHDL/Verilog |
17 |
| IIT Madras |
February 22-26,2010 |
Algorithms to Architectures |
17 |
| IIT Kharagpur |
March
2-13,2010 |
Low-Power,High Speed Digital Subsystem Design : Spec to Test |
14 |
NIT Trichy
(Organised by IIT Madras) |
Sept.29th - Oct.2nd,2010
|
Chip Integration and Tapeout Issues |
27 |
MNIT Jaipur
(Organised by CEERI Pilani) |
Dec.13th - 17th, 2010
|
Semiconductor Memory
Design & Test |
52 |
| IIT Kharagpur |
March 6th - 12th , 2011 |
VLSI aspects on Biomedical
Engineering |
22 |
| IIT Delhi |
March 14th - 19th, 2011
|
Low Power, Low Noise
Operational Amplifier Design |
20 |
VNIT Nagpur
(Organised by IIT Bombay) |
Oct. 8th - 10th, 2011
|
Design Finishing for Chip Tape Out |
25 |
IIT Madras,
IISc. Bangalore,
IIT Delhi |
Dec. 9th - 12th, 2011
|
Analog/Mixed Signal Design
|
|