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Lectures - IEP Program at IIT Kanpur on Synthesis of Digital System

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1.
 Verilog Language Concepts Day 1 PPT
2.
 Digital Design Flow PPT
3.
 Verilog Language Concepts Day 2 PPT
4.
 Combinational Circuits PPT
5.
 Adder Circuits PPT
6
 FSM and Efficient Synthesizable Day 3 PPT
7.
Sequential Circuit Description
PPT
8.
 Sequential Circuits PPT
9.
 Multipliers and Shifters Day 4 PPT click here
10.
 Sequential Circuit Synthesis PPT click here
11. RT Level Design Day 5 PPT click here
12. Sequential Circuit Synthesis - II PPT click here
13. Formal Verification-3 ROBDD Day 6 PDF click here
14. VLSI Testing-1 PDF click here
15. VlSI Testing-2 PDF click here
16. FP-Numbers & Multipliers Day 7 PPT click here
17. High-Level Synthesis - I PPT click here
18. High-Level Synthesis-II Day 8 PPT click here
19. Partitioning PPT click here
20. Pipelined Circuit Synthesis Day 9 PPT click here
21. Power Aware Synthesis PPT click here
22. ALU Day 10 PPT click here
23. Synthesis for Test PPT click here
24. Testability PPT click here
25. Synthesis for Test Day 11 PPT click here
26. Design for Testability PPT click here
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